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Bradley J Garni

from Austin, TX
Age ~61

Bradley Garni Phones & Addresses

  • 1503 32Nd St, Austin, TX 78703 (512) 542-9853
  • 1503 W 32Nd St, Austin, TX 78703 (512) 542-9853
  • 4532 Eagle Feather Dr, Austin, TX 78735 (512) 899-2740
  • 1303 Broadmoor Dr, Austin, TX 78723
  • New Berlin, WI
  • Dyer, TN
  • Madison, WI

Publications

Us Patents

Three Input Sense Amplifier And Method Of Operation

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US Patent:
6580298, Jun 17, 2003
Filed:
Jun 28, 2002
Appl. No.:
10/186363
Inventors:
Chitra K. Subramanian - Austin TX
Bradley J. Garni - Austin TX
Joseph J. Nahas - Austin TX
Thomas W. Andre - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 706
US Classification:
327 55, 327 74, 327 52
Abstract:
A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors ( and ) and loads ( and ) are used in conjunction with current steering circuitry ( and ) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT B) to reflect the difference between the two current differential quantities.

Accelerated Life Test Of Mram Cells

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US Patent:
6894937, May 17, 2005
Filed:
Sep 26, 2003
Appl. No.:
10/672959
Inventors:
Bradley J. Garni - Austin TX,
Thomas W. Andre - Austin TX,
Joseph J. Nahas - Austin TX,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C029/00
US Classification:
365201, 36518909, 36518523, 327530
Abstract:
A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

Circuit And Method For Reading A Toggle Memory Cell

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US Patent:
2004000, Jan 15, 2004
Filed:
Jun 28, 2002
Appl. No.:
10/184811
Inventors:
Bradley Garni - Austin TX,
Thomas Andre - Austin TX,
Joseph Nahas - Austin TX,
Chitra Subramanian - Austin TX,
International Classification:
G11C011/14
US Classification:
365/171000
Abstract:
A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (). The first signal is compared to the second signal to determine the state of the MRAM cell.

Integrated Circuit Having Low Power Mode Voltage Regulator

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US Patent:
8319548, Nov 27, 2012
Filed:
Nov 19, 2009
Appl. No.:
12/622277
Inventors:
David R. Bearden - Austin TX,
Kenneth R. Burch - Austin TX,
Charles E. Seaberg - Austin TX,
Hector Sanchez - Cedar Park TX,
Bradley J. Garni - Austin TX,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G05F 1/10
US Classification:
327544, 327540
Abstract:
A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Mram Architecture With Electrically Isolated Read And Write Circuitry

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US Patent:
7154772, Dec 26, 2006
Filed:
Mar 9, 2005
Appl. No.:
11/076523
Inventors:
Joseph J. Nahas - Austin TX,
Thomas W. Andre - Austin TX,
Chitra K. Subramanian - Austin TX,
Bradley J. Garni - Austin TX,
Mark A. Durlam - Chandler AZ,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 11/00
US Classification:
365158, 365 97, 36523006, 257411
Abstract:
A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Mram Sense Amplifier Having A Precharge Circuit And Method For Sensing

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US Patent:
7038959, May 2, 2006
Filed:
Sep 17, 2004
Appl. No.:
10/943579
Inventors:
Bradley J. Garni - Austin TX,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/00
US Classification:
365203, 365204, 365207, 365210
Abstract:
A sense amplifier () and method for sensing a MRAM cell () is provided. The sense amplifier () includes a precharge circuit (′) having an operational amplifier () that uses a voltage divider () in a feedback path to control the amount of charge stored on a capacitor (). During a precharge portion of a read operation, the charge stored on the capacitor () is used to precharge the sense amplifier (). By using charge sharing to precharge the sense amplifier (), the sense amplifier () can be precharged to a steady state common mode voltage more quickly, thus decreasing time required for a read operation.

Mram And Methods For Reading The Mram

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US Patent:
6909631, Jun 21, 2005
Filed:
Oct 2, 2003
Appl. No.:
10/679134
Inventors:
Mark A. Durlam - Chandler AZ,
Thomas W. Andre - Austin TX,
Mark F. DeHerrera - Tempe AZ,
Bradley N. Engel - Chandler AZ,
Bradley J. Garni - Austin TX,
Joseph J. Nahas - Austin TX,
Nicholas D. Rizzo - Gilbert AZ,
Saied Tehrani - Tempe AZ,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C011/14
US Classification:
365158, 365173
Abstract:
An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Mram Architecture With Electrically Isolated Read And Write Circuitry

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US Patent:
6903964, Jun 7, 2005
Filed:
Jun 28, 2002
Appl. No.:
10/185868
Inventors:
Joseph J. Nahas - Austin TX,
Thomas W. Andre - Austin TX,
Chitra K. Subramanian - Austin TX,
Bradley J. Garni - Austin TX,
Mark A. Durlam - Chandler AZ,
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C011/00
US Classification:
365158, 36518904
Abstract:
A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
Bradley J Garni from Austin, TX, age ~61 Get Report